Epson LX-86TM Especificações descarregar pdf (Página 54)

REV.-A

2.4.4 Reset Circuit

A reset operation is performed when the INIT signal is input from the interface and when the printer

power is turned on. (Refer to Sections 1.4.6, 2.4.1, 2.4.2, and 2.4.3.1 for the reset operation.) Figure

2-17 shows the reset circuit.

E05A03 (3B)

R63

‘:;’’’”3’)+

INIT

C27

(CN2, Pin8)

470p

INIT

----

l—

RESI

~----

AND

—-

--—

RESO

+24

+AJ--c3

R43

ZD2

HZS1 5-3

47K

+-+

R42

+ D5

R34

MA165

12K

C15

p/5ov

RESET (CPU, Pin 28)

*m(cN2pin’3)

(lC)

Fig. 2-17. Reset Circuit

The I NIT signal from which noise is attenuated by

R63 and C27 is input to the

E05A03.

The

RESI

terminal

of the

E05A03

is connected to the power supply

5 V and +24

reset circuit. When the printer power

is turned on, the level of the

RESI

signal is held at its threshold level or below (LOW level) until the voltage

of the +24 V line reaches the Zener voltage of ZD2 (when the power is turned off, the sequence

reverses). The same sequence is followed for the + 5 V line. The level of the

RESI

signal is held at its

threshold level or below (LOW level) until the voltage of the +5 V line reaches +5 V. In addition, the

level of the

RESI

signal is held LOW by R43 and C 15 for approximately 47 ms after the power supply

voltages become stable. The Schmitt trigger gate (CMOS level) at the input terminal of the

RESI

signal

shapes the analog waveform. The

INIT and

RESI

signals are ANDed in the

E05A03,

then output from

the

RESO

terminal to the RESET terminals of the CPU and the interface board.

2-22

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