Epson LX-86TM Especificações Página 44

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REV.-A
Table 2-3. CPU Port Assignment (cent’d)
Pin
Port
,,0
Signal Line
Number Assignment
Name
Description
25
NMI
I
Non-maskable interrupt input.
The interrupt routine is executed
at the trailing edge of this signal. This pin is invalid because it
is tied to ground.
26
INT
1
I
Interrupt input. The interrupt routine is executed at the leading
edge of this signal. This pin is invalid because it is tied to
ground.
27
MODE 1
I
External memory space setting port. MODES 1 and O (pin 29)
are both pulled up to HIGH so that an external memory of 64K
bytes (addresses O through
FFFFH)
can be used.
28
RESET
I
RESET
Reset terminal. When this signal is LOW, the printer is reset,
and ports A through C and D are set to be high impedance
input ports, and port F is set to be an address output (start
address OH).
29
MODE O
I
Refer to pin 27, MODE 1.
30
x2 CPU external clock input. This printer is driven with a 14.74
I
31
xl
MHz clock. The operation codes are fetched at approximately
1.3 MHz, and memory read/write operations are performed at
approximately 1.6 MHz.
32
Vss
-
Ground terminal.
33
AV
SS
Ground terminal for the A/D converter in the CPU.
34
ANO
SW2-1
Analog input port of the 8-bit A/D converter in the CPU. Reads
1
i
I
1
the states of DIP SW2-1 through SW2-3.
36
AN2
SW2-3
37
AN3
I
SW2-4 Analog input port of the 8-bit A/D converter in the CPU. Reads
the state of DIP
SW2-4. This signal line is connected to the
AUTO FEED XT signal line of the interface. When DIP
SW2-4
is ON, the automatic paper feed function is valid. When the
DIP switch is OFF, this function is controlled by a signal from
the host computer (not fixed).
38
AN4
I
Analog input port for the 8-bit A/D converter in the CPU.
Reads the
SLCT
IN signal from the interface. When the
SLCT-
~ signal is HIGH, DC
l/DC3
control from the host computer is
valid. When it is LOW, DC
l/DC3
control is ignored, and the
printer is always selected as a device. (The signal can be tied
LOW using jumper J 1.)
39
AN5
I
+24 Analog input port for the 8-bit A/D converter in the CPU.
Monitors the +24 V voltage and controls the printhead drive
pulse width.
40
AN6 -
Not used.
41
AN7 -
Not used.
42
VAREF
I
Reference voltage input for the 8-bit A/D converter in the CPU.
43 AV
CC
I
Power supply input for the 8-bit A/D converter in the CPU.
44
m
o
m
Memory read timing strobe signal. Connected to the RD strobe
terminal of the gate array and the output enable terminal of
the ROM and RAM.
2-12
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