Epson LX-86TM Especificações descarregar pdf (Página 131)

REV.-A

. CPU Timing (Figures A-3 through A-5)

Three oscillations define one state. The OP code fetch requires four states: during T1 to

T3, program

memory is read; instructions are interpreted during

T4. Address bus lines 15 - 8 are output from

to T4. Address bus lines 7 - 0

(PD7

O) are used in the multiplex mode; the address is latched during

at the ALE signal. Since the memory addressed is enabled after disengaging the driver

(AD7

- O),

is output from

T3, fetched at T3, and processed internally at T4. The ALE and

signals are

executed from T1 -

T3; the OP code fetch for these two signals is performed at T4. The WR signal

is output from the middle of

to the beginning of T3. The address and ALE timing is the same as

that for memory read; however, following address output bus lines

AD7 -0 (pD7 - O) are not disabIed,

and write data is output at

AD7 -

0 at the beginning of

and the end of T3.

NOTE: When lines

PD7

0 are set to the multiplexed

addressldata bus

(AD7

- O), and

PF7

-0 to

the address bus (AB7 -

O), the

and WR signals in the machine cycle are high when memory

is not being accessed.

CLOCK

ALE

AB15 -8

(PF7

-O)

AD7 -0

(PD7

-O)

ADDRESS

}--

--<

OP CODE

>---c

Fig. A-3. OP Code Fetch Timing

CLOCK

AB15 -8

(PF7

-O)

ADDRESS

AD7 -0

(PD7

-O)

ADDRESS

{

READ DATA

>---

‘~

Fig. A-4. Memory Read Timing

CLOCK

AB15 -8

(PF7

-O)

ADDRESS

AD7 -0

(PD7

-O)

ADDRESS

WRITE DATA

‘~

Fig. A-5. Memory Write Timing

A-6

1 2 ... 126 127 128 129 130 131 132 133 134 135 136 ... 141 142

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