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2.4.1 Functions of the CPU
The core of the control circuit is the 78 10H CPU
(IC2B).
Table 2-3 shows the function of each pin and
the related circuits.
Table 2-3. CPU Port Assignments
Pin
Number
Port
Assignment
1/0
Signal Line
Name
Description
1/0
port. Switches the carriage motor drive voltage and the
holding voltage. When this signal is HIGH (LOW), the drive
voltage (holding voltage) is applied to the carriage motor.
Not used.
1
PAO
o
CRCOM
2
3
PA1
—
PA2
o
PFCOM
1/0 port. Switches the paper feed motor drive voltage and the
holding voltage. When this signal is HIGH (LOW),
the drive
voltage (holding voltage) is applied to the paper feed motor.
LF SW
1/0 port. Reads the state of the LINE FEED switch on the
control panel.
1/0 port. Reads the state of the FORM FEED switch on the
control panel.
4
PA3
I
I
FF
SW
PA4
‘-5
6 PA5
I
PE SW 1/0 port. Reads the state of the paper end sensor. When no
paper is loaded, this signal goes LOW.
Not used.
7
PA6
—
P/s
SW1 -8
1
Swl
- 1
TXD
1/0 port. Reads the P/~ signal from the optional interface.
1/0 port. Reads the state of DIP SW1.
8
9
t
16
17
18
19
PA7
PBO
!
PB7
Pco
I
I
o
I
TXD output port. Outputs the data from the serial 1/0 channel
in the CPU to the
TXD (transmit data to the host computer)
terminal of the optional interface.
Pcl
RXD
RXD
input port. Used as a receive control signal when the
optional serial interface board (for serial/parallel data conver-
sion) is connected. (Data reception detection)
ONLINE LP
PC2
o
1/0 port. Controls the ON LINE LED on the control panel. When
this signal is LOW, the LED lights.
ONLINE
SW
INT2 input port. Reads the state of the ON LINE switch on the
control panel. Connected to the interrupt controller in the CPU,
which executes the ON LINE/OFF LINE switch interrupt routine
when this signal is LOW.
20
PC3
I
Em
21
PC4
o
1/0 port. Outputs an error signal to the interface board when
the printer is in an error state. When this signal is LOW, the
printer is in an error state.
ACKNLG
22
23
24
PC5
o
0
0
1/0 port. Outputs the acknowledge signal to the interface. This
signal is LOW active.
COO output port. Outputs the drive pulse width signal, which is
determined by the timer/event counter in the CPU, to the FIRE
terminal of gate array E05A03. This
signal is LOW active.
PC6
FIRE
PC7
BUZZER
1/0 port. Outputs the buzzer signal to the control panel. When
this signal is LOW, the buzzer rings.
2-11
- TECHNICAL MANUAL 1
- PRECAUTIONS 3
- REVISION SHEET 5
- TABLE OF CONTENTS 6
- CHAPTER 1 7
- GENERAL DESCRIPTION 7
- FEATURES 9
- 1.2 INTERFACE 11
- 1.3 SPECIFICATIONS 14
- 1.4 OPERATING CONTROLS 20
- Middle and 21
- 1.5 MAIN COMPONENTS 26
- CHAPTER 2 30
- OPERATING PRINCIPLES 30
- 2.1 GENERAL 33
- MODEL-3A1O PRINTER MECHANISM 34
- (MAIN BOARD) 34
- 2.3 POWER SUPPLY CIRCUIT 35
- 2.3.2 Regulator Circuit 37
- 2.4 CONTROL CIRCUIT 41
- (ControIl 46
- 1. Address latch 47
- -“’’’’’’’’’’’’’;’’’”:l 51
- *m(cN2pin’3) 54
- 2.4.6 Paper Feed Motor 59
- ~---vuvu 61
- 61
- EPSON LX-800 62
- 2.4.8 Print Timing Control 66
- 4,,1<,1 68
- 2.5.1 Sensor Mechanism 69
- Carriage Guide Shaft 70
- Paper Feed Motor 72
- Breaking 74
- CHAPTER 3 75
- OPTIONAL EQUIPMENT 75
- 3.1 GENERAL 76
- 3.2 OPTIONAL INTERFACES 76
- CHAPTER 4 77
- ISASSEMBLY, ASSEMBLY, AND 77
- ADJUSTMENT 77
- 4.2 DISASSEMBLY AND ASSEMBLY 82
- 4.2.2 Removal of Cases 83
- Flat Spring 92
- , Platen 92
- Platen Gear 92
- Carriaga Guide 93
- Shaft Ground 93
- Sprocket Shaft 98
- Guide Roller’ 98
- Sprocket Wheel 98
- 4.3 ADJUSTMENT 99
- ,’v?,?la 100
- CHAPTER 5 101
- TROUBLESHOOTING 101
- LIST OF FIGURES 101
- LIST OF TABLES 101
- ‘ARN’NG~ 102
- I printer mechanism 104
- Set the gap-adjustment lever 107
- Printhead 111
- 5.3 UNIT REPAIR 112
- ● The l/F cable is 113
- Solution 113
- 5.3.2 Printer Mechanism 115
- ● Replace the 116
- ● Resistance value: 117
- ● Sheet load 118
- ● Remove any 118
- CHAPTER 6 120
- MAINTENANCE 120
- 6.1 PREVENTIVE MAINTENANCE 121
- Adhesive Application Point 122
- No. of Point 122
- APPENDIX 124
- A.1 PRINCIPAL 126
- SPECIFICATIONS 126
- Fig. A-2. wPD7810/7811 Block 128
- E05A03BA 132
- (E05A03CA) 132
- Gate Array 132
- Memory Ce I 134
- A.1.4 494 Regulator IC 135
- A.1.5 7407 137
- Fig. A-1 2. 7407 Pin Diagram 137
- A.2 SCHEMATICS AND DIAGRAMS 138
- Fig, A-15 139
- Board Component Layout 139
- in Japan 142
- 87.07 -.6 142
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