Epson SED 1520 Series Especificações descarregar pdf (Página 14)

S1D15300 Series

5–2 EPSON Rev.1.4

3. BLOCK DIAGRAM (S1D15300D00B

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O0 O99

···············································

O100 O15

·····················

V

2

V4

VDD

VSS

V1

V3

V5

CAP1+

CAP1–

CAP2+

CAP2–

CAP3–

FRS

FR

CL

DYO

DOF

M//S

Segment driver Common driver

Shift register

Power supply

circuit

I/O buffer circuit

132 x 65-dot

display data RAM

Display data latch

Line address decoder

Line counter

Initial display line register

Page address

register

Column address decoder

8-bit column address counter

8-bit column address register

Display timing

generator circuit

Bus holder

Status

register

Oscillator

Microprocessor interface I/O buffer

COMS

COM S

Output

status

selector

circuit

VS1

CS1 CS2 A0 RD

(E)

WR

(R/W)

C86 P/S RES D7

(SI)

D6

(SCL)

D5 D4 D3 D2 D1 D0

Command decoder

VOUT

VR

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 53 54

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